1. Technical Field
Embodiments of the present invention relate to a semiconductor integrated circuit, and more particularly, to an anti-fuse control circuit for a semiconductor integrated circuit.
2. Related Art
Generally, in a semiconductor integrated circuit, a fuse used after packaging is typically referred to as an anti-fuse. The reason is that the fuse before the packaging performs a repair by cutting but the fuse used after packaging performs a repair by interconnection rather than by the cutting. That is, the anti-fuse is a term that refers to the fuse before packaging. This means a fuse that is electrically opened in a normal state and is electrically shorted when an insulator between conductors is broken due to application of high voltage.
FIG. 1 is a circuit diagram of a general anti-fuse control circuit.
In FIG. 1, the anti-fuse control circuit may be configured to include a first inverter IV1 that inverts and outputs a power up signal PWRUP, a first PMOS transistor P1 that is connected between a terminal for applying external power supply voltage Vext and a first node nd1 that receives an output signal of the first inverter IV1 through a gate thereof. The anti-fuse control circuit may also comprise a second PMOS transistor P2 that is connected between the terminal for applying the external power supply voltage Vext and the first node nd1 and the second PMOS transistor P2 which may receive a program signal PG through a gate thereof. The anti-fuse control circuit may also comprise a third PMOS transistor P3 that is connected between the first node nd1 and an anti-fuse F1 and the third PMOS transistor P3 may receive ground voltage Vss through a gate thereof. Still further, anti-fuse control circuit may comprise a third NMOS transistor N3 that is connected between the first node nd1 and the anti-fuse F1 to receive power supply voltage Vbba through a gate thereof and apply back bias voltage Vbbf to a bulk terminal.
In addition, the output terminal of the first node nd1 is formed with fourth and fifth PMOS transistors P4 and P5 and first and second NMOS transistors N1 and N2 in a cross-coupled structure and comprises a first latch unit R1 including second and third inverters IV2 and IV3. Further, a fourth inverter IV4 inverts an output of the first latch unit R1 to output an output signal anti_anz.
An operation process of the anti-fuse control circuit according to the related art will be described below in terms of a program mode and a general operation mode with reference to FIG. 1.
First, the program mode. When the program signal PG is a low level and the anti-fuse F1 is broken, the second PMOS transistor P2 is turned on. In addition, when the power up signal PWRUP is a low level, the first PMOS transistor P1 is turned off, such that the first node nd1 is set to be the level of the external power supply voltage Vext.
In this case, the level of the back bias voltage Vbbf is set to be −3V or less that is low back gate bias (LVBB). Here, the low back gate bias (LVBB) is voltage supplied from an internal voltage generator.
Generally, the anti-fuse control circuit is in a short state in which resistance is very small while the insulator of the anti-fuse F1 is broken at the time of the program mode operation.
Next, the general operation mode. In general operation mode the program signal PG is set to the high level, such that the voltage value of the first node nd1 is defined by the power up signal PWRUP. In this case, the back bias voltage Vbbf is set to be the level of the ground voltage Vss. Further, the voltage level of the power supply voltage Vbba is set to be the level of the external power supply voltage Vext to turn on the third NMOS transistor N3.
In this case, when the anti-fuse F1 is not programmed, the high level of the first node nd1 is maintained by the first latch unit R1 and the logic level of the output signal anti_anz is set to the low level by the fourth inverter IV4.
On the other hand, when the anti-fuse F1 is programmed, the voltage level of the back bias voltage Vbbf becomes the level of the ground voltage Vss. In this case, when the power up signal PWRUP is shifted to a low level, the voltage of the first node nd1 becomes the low level and thus, the signal of the high level stored in the first latch R1 becomes the low level. Therefore, an output signal of the first latch R1 is inverted by the fourth inverter IV4 and thus, the output signal anti_anz is output as the high level.
However, when the anti-fuse F1 is a general operation mode, the third PMOS transistor P3 and the third NMOS transistor N3 are in a turn on state at all times, such that the voltage of the first node nd1 is supplied to the anti-fuse F1 at all times. When the anti-fuse F1 is not programmed, even though the voltage of the first node nd1 is supplied to the anti-fuse F1 at all times in the general operation mode, the anti-fuse F1 is in an open state to prevent current leakage or malfunction due to current leakage. However, when the anti-fuse F1 is programmed, in the general operation mode, the anti-fuse F1 has a high resistance value due to the process change such that the current leakage occurs and a malfunction due to current leakage is caused.